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M16C/62P Group (M16C/62P, M16C/62PT)
7.2 Setting Processor Modes
Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Table 7.2 shows the processor mode after hardware reset. Table 7.3 shows the PM01 to PM00 bit set
values and processor modes.
Table 7.2 Processor Mode After Hardware Reset
CNVSS Pin Input Level
VSS
(1, 2)
VCC1
NOTES :
1. If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1
or hardware reset 2), the internal ROM cannot be accessed regardless of PM10 to PM00 bits.
2. The multiplexed bus cannot be assigned to the entire CS space.
Table 7.3 PM01 to PM00 Bits Set Values and Processor Modes
TaS : Ta.9
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Single-Chip Mode
Microprocessor Mode
page 42
f o
3
6
4
Processor Mode
7. Processor Mode
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