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M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
(Common to setting with wait and setting without wait)
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
(1)
P5_0 to P5_2
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
Measuring conditions :
• V
=V
CC1
CC2
• Input timing voltage : Determined with V
• Output timing voltage : Determined with V
Figure 23.15 Timing Diagram (3)
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
t
su(RDY–BCLK)
t
t
su(HOLD–BCLK)
t
d(BCLK–HLDA)
=3V
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f o
3
6
4
23. Electrical Characteristics (M16C/62P)
h(BCLK–HOLD)
t
d(BCLK–HLDA)
Hi–Z
=0.6V, V
=2.4V
IL
IH
=1.5V, V
OL
OH
V
= V
CC1
CC2
t
h(BCLK–RDY)
=1.5V
= 3V
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