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M16C/62P Group (M16C/62P, M16C/62PT)
Figure 17.31 SIM Interface Connection
17.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to "1".
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TXD2 output low with the timing shown in Figure 17.32. If the R2RB register is read while
outputting a parity error signal, the PER bit is cleared to "0" and at the same time the TXD2 output is
returned high.
When transmitting, a transmission-finished interrupt request is generated at the falling edge of the
transfer clock pulse that immediately follows the stop bit. Therefore, whether a parity signal has been
returned can be determined by reading the port that shares the RXD2 pin in a transmission-finished
interrupt service routine.
Transfer
clock
RXD2
TXD2
U2C1 register
RI bit
This timing diagram applies to the case where the direct format is
implemented.
NOTES :
1. The output of microcomputer is in the high-impedance state
(pulled up externally).
Figure 17.32 Parity Error Signal Output Timing
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Microcomputer
TXD2
RXD2
"H"
"L"
"H"
ST
D0
"L"
"H"
"L"
"1"
"0"
page 200
f o
3
6
4
SIM card
D1
D2
D3
D4
D5
(NOTE 1)
17. Serial I/O
D6
D7
P
SP
ST : Start bit
P : Even Parity
SP : Stop bit
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