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M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.1 Pin Status When RESET Pin Level is "L"
Pin Name
P0
P1
P2, P3, P4_0 to P4_3
P4_4
P4_5 to P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7
P6, P7, P8_0 to P8_4,
P8_6, P8_7, P9, P10
P11, P12, P13,
(2)
P14_0, P14_1
NOTES :
1. Shown here is the valid pin state when the internal power supply voltage has stabilized after power-on.
When CNVSS = VCC1, the pin state is indeterminate until the internal power supply voltage stabilizes.
2. P11, P12, P13, P14_0, P14_1 pins exist in 128-pin version.
b15
Figure 5.3 CPU Register Status After Reset
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
____________
CNVSS = VSS
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
b15
0000h
0000h
0000h
0000h
0000h
0000h
0000h
b19
00000h
Content of addresses FFFFEh to FFFFCh
b15
0000h
0000h
0000h
b15
0000h
b8
b7
IPL
U
I
O
page 34
f o
3
6
4
Status
BYTE = VSS
Data input
Data input
Address output (undefined)
CS0 output ("H" is output)
Input port (
)
Pulled high
WR output ("H" is output)
BHE output (undefined)
RD output ("H" is output)
BCLK output
HLDA output (The output value
depends on the input to the
HOLD pin)
HOLD input
ALE output ("L" is output)
RDY input
Input port
Input port
b0
Data Register(R0)
Data Register(R1)
Data Register(R2)
Data Register(R3)
Address Register(A0)
Address Register(A1)
Frame Base Register(FB)
b0
Interrupt Table Register(INTB)
Program Counter(PC)
b0
User Stack Pointer(USP)
Interrupt Stack Pointer(ISP)
Static Base Register(SB)
b0
Flag Register(FLG)
b0
B
S
Z
D
C
(1)
CNVSS = VCC1
BYTE = VCC
Data input
Input port
Address output (undefined)
CS0 output ("H" is output)
Input port (
Pulled high
WR output ("H" is output)
BHE output (undefined)
RD output ("H" is output)
BCLK output
HLDA output (The output value
depends on the input to the
HOLD pin)
HOLD input
ALE output ("L" is output)
RDY input
Input port
Input port
5. Reset
)
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