Renesas M16C/62P Hardware Manual page 191

M16C/62P Group (M16C/62P, M16C/62PT)
17.1.2.2 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures
below.
• Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to "0" (reception disabled)
(2) Set the RE bit in the UiC1 register to "1" (reception enabled)
• Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register "000b" (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register "001b", "101b", "110b".
(3) "1" is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiCi
register
17.1.2.3 LSB First/MSB First Select Function
As shown in Figure 17.17, use the UFORM bit in the UiC0 register to select the transfer format. This
function is valid when transfer data is 8 bits long.
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
CLK
i
TXDi
RXDi
(2) When the UFORM bit = 1 (MSB first)
CLK
i
TXDi
RXDi
NOTES :
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiLCH bit in the UiC1
register = 0 (no reverse), the STPS bit in the UiMR register = 0
(1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled).
Figure 17.17 Transfer Format
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
ST D0 D1 D2
ST D0 D1 D2
ST D7 D6 D5
ST D6 D5
D7
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f o 3 6 4
D3 D4 D5 D6
D3 D4 D5 D6
D4 D3 D2 D1
D4 D3 D2 D1
17. Serial I/O
D7 P SP
D7 P SP
D0 P SP
D0
P SP
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2