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M16C/62P Group (M16C/62P, M16C/62PT)
VCC1, VCC2
XIN
t
d(P-R)
Microprocessor
mode BYTE = H
RESET
BCLK
Address
RD
WR
CS0
Microprocessor
mode BYTE = L
Address
RD
WR
CS0
Single chip
mode
Address
Figure 5.2 Reset Sequence
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
More than
20 cycles
are needed
BCLK
page 33
f o
3
6
4
28cycles
FFFFDh
FFFFCh
FFFFCh
FFFFCh
Content of reset vector
FFFFEh
Content of reset vector
FFFFEh
Content of reset vector
FFFFEh
5. Reset
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