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M16C/62P Group (M16C/62P, M16C/62PT)
System Clock Control Register 0
b7
b6
b5
b4
b3
b2
b1
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. The CM03 bit is set to "1" (high) while the CM04 bit is set to "0," or when entered to stop mode.
3. This bit is provided to stop the main clock when the low power dissipation mode or on-chip oscillator low power dissipation
mode is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock,
set bits in the following order.
(a) Set the CM07 bit to "1" (Sub-clock select) or the CM21 bit of CM2 register to "1" (On-chip oscillator select) with the
sub-clock stably oscillating.
(b) Set the CM20 bit of CM2 register to "0" (Oscillation stop, re-oscillation detection function disabled).
(c) Set the CM05 bit to "1" (Stop).
4. During external clock input, Set the CM05 bit to "0" (oscillate).
5. When CM05 bit is set to "1", the XOUT pin goes "H". Furthermore, because the internal feedback resistor remains connected,
the XIN pin is pulled "H" to the same level as XOUT via the feedback resistor.
6. After setting the CM04 bit to "1" (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from "0" to "1" (sub-clock).
7. When entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip oscillator low power mode,
the CM06 bit is set to "1" (divide-by-8 mode).
8. The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to "1" (peripheral clock
turned off when in wait mode).
9. To use a sub-clock, set this bit to "1". Also make sure ports P8_6 and P8_7 are directed for input, with no pull-ups.
10. When the PM21 bit of PM2 register is set to "1" (clock modification disable), writing to the CM02, CM05, and CM07 bits has
no effect.
11. If the PM21 bit needs to be set to "1," set the CM07 bit to "0" (main clock) before setting it.
12. To use the main clock as the clock source for the CPU clock, set bits in the following order.
(a) Set the CM05 bit to "0" (oscillate).
(b) Wait the main clock oscillation stabilizes.
(c) Set the CM11, CM21 and CM07 bits all to "0".
13. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1"
(divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
14. To return from on-chip oscillator mode to high-speed or middle-speed mode, set the CM06 and CM15 bits both to "1".
Figure 10.2 CM0 Register
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
(1)
b0
Symbol
CM0
Bit Symbol
CM00
Clock Output Function
Select Bit
(Valid only in single-chip
CM01
mode)
WAIT Mode Peripheral
CM02
Function Clock Stop Bit
XCIN-XCOUT Drive
CM03
Capacity Select Bit
Port XC Select Bit
CM04
Main Clock Stop Bit
CM05
(3, 10, 12, 13)
Main Clock Division
CM06
Select Bit 0
System Clock Select Bit
CM07
(6, 10, 11, 12)
page 67
f o
3
6
4
Address
After Reset
0006h
01001000b
Bit
Name
b1 b0
0 0 : I/O port P5_7
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
0 : Do not stop peripheral function clock in wait mode
(10)
1 : Stop peripheral function clock in wait mode
0 : LOW
(2)
1 : HIGH
(2)
0 : I/O port P8_6, P8_7
1 : XCIN-XCOUT generation function
0 : On
1 : Off
(4, 5)
0 : CM16 and CM17 valid
(7, 13, 14)
1 : Division by 8 mode
0 : Main clock, PLL clock, or on-chip oscillator clock
1 : Sub-clock
10. Clock Generating Circuit
Function
(8)
(9)
RW
RW
RW
RW
RW
RW
RW
RW
RW
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