Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
Count source
Measurement pulse
Timing at which counter
reaches "0000h"
TBiS bit
IR bit in
TBiIC register
MR3 bit in
TBiMR register
NOTES :
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "00b" (measure the interval
from falling edge to falling edge of the measurement pulse).
Figure 15.21 Operation Timing when Measuring a Pulse Period
Count source
Measurement pulse
Reload register
transfer timing
Timing at which counter
reaches "0000h"
TBiS bit
IR bit in
TBiIC register
MR3 bit in
TBiMR register
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits
are assigned to the bit 5 to bit 7 TBSR register.
i = 0 to 5
NOTES :
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "10b" (measure the
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of
the measurement pulse).
Figure 15.22 Operation Timing when Measuring a Pulse Width
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
"H"
"L"
"0"
"1"
"0"
"1"
"0"
"H"
"L"
counter
"1"
"0"
"1"
"0"
Set to "0" upon accepting an interrupt request or by
writing in program
"1"
"0"
page 143
f o
3
6
4
Transfer
(indeterminate value)
(NOTE 1)
Transfer
Transfer
Transfer
(indeterminate
(measured value)
(measured
value)
value)
(NOTE 1)
(NOTE 1)
(NOTE 1)
15. Timers
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
(NOTE 2)
Advertisement
Table of Contents
