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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.4.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit
in the UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transfer clock polarity and phase are the same for the master and salves to be commu-
nicated.
Figure 17.26 shows the transmission and reception timing in master (internal clock).
Figure 17.27 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 17.28 shows the transmission and reception timing (CKPH=1) in slave (external clock).
Clock output
(CKPOL=0, CKPH=0)
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
Clock output
(CKPOL=1, CKPH=1)
Data output timing
Data input timing
Figure 17.26 Transmission and Reception Timing in Master Mode (Internal Clock)
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
D0
"L"
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f o
3
6
4
D1
D2
D3
D4
17. Serial I/O
D5
D6
D7
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