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M16C/62P Group (M16C/62P, M16C/62PT)
24.8.1.4 Timer A (Pulse Width Modulation Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i
= 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR
register before setting the TAiS bit in the TABSR register to "1" (count starts).
Always make sure the TAiMR register, TA0TGL and TA0TGH bits and the TRGSR register are modi-
fied while the TAiS bit remains "0" (count stops) regardless whether after reset or not.
The IR bit is set to "1" when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
To use the Timer Ai interrupt (interrupt request bit), set the IR bit to "0" by program after the above
listed changes have been made.
When setting TAiS register to "0" (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output "H," output level is set to "L" and the IR bit is set to "1".
• When TAiOUT pin is output "L," both output level and the IR bit remains unchanged.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-
phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins
go to a high-impedance state.
R
e
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2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
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0
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0
1
8
5
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2
3
0
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3
6
4
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24. Usage Precaution
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