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M16C/62P Group (M16C/62P, M16C/62PT)
15.2.3 Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 15.8). Figure 15.20 shows TBiMR register in pulse period and pulse width
measurement mode. Figure 15.21 shows the operation timing when measuring a pulse period. Figure
15.22 shows the operation timing when measuring a pulse width.
Table 15.8 Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count Source
Count Operation
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TBiIN Pin Function
Read from Timer
Write to Timer
NOTES:
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts
counting.
3. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TBSR register.
Timer Bi Mode Register (i=0 to 5)
b7
b6
b5
b4
b3
NOTES:
1. This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to "0" (no overflow) by writing
to the TBiMR register at the next count timing or later after the MR3 bit was set to "1" (overflowed). The MR3 bit cannot be set to
"1" in a program. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits are
assigned to the bit 5 to bit 7 in the TBSR register.
Figure 15.20 TBiMR Register in Pulse Period and Pulse Width Measurement Mode
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of mea-
surement pulse. The counter value is set to "0000h" to continue counting.
Set TBiS (i=0 to 5) bit
Set TBiS bit to "0" (= stop counting)
• When an effective edge of measurement pulse is input
• Timer overflow. When an overflow occurs, MR3 bit in the TBiMR register is set
to "1" (overflowed) simultaneously. MR3 bit is set to "0" (no overflow) by
writing to TBiMR register at the next count timing or later after MR3 bit was
set to "1". At this time, make sure TBiS bit is set to "1" (start counting).
Measurement pulse input
Contents of the reload register (measurement result) can be read by reading
(2)
TBi register
Value written to TBi register is written to neither reload register nor counter
Symbol
b2
b1
b0
TB0MR to TB2MR
039Bh to 039Dh
1
0
TB3MR to TB5MR
035Bh to 035Dh
Bit Symbol
Bit Name
TMOD0
Operation Mode
Select Bit
TMOD1
MR0
Measurement Mode
Select Bit
MR1
MR2
TB0MR and TB3MR registers
Set to "0" in pulse period and pulse width measurement mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0". When read, its content turns out to be
indeterminate.
Timer Bi Overflow
MR3
(1)
Flag
TCK0
Count Source
Select Bit
TCK1
page 142
f o
3
6
4
Specification
(3)
to "1" (= start counting)
Address
After Reset
00XX0000b
00XX0000b
Function
b1 b0
1 0 : Pulse period / pulse width
measurement mode
b3 b2
0 0 : Pulse period measurement
(Measurement between a falling edge and the next
falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the next
rising edge of measured pulse and between a rising
edge and the next falling edge)
1 1 : Do not set to this value
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
15. Timers
(1)
RW
RW
RW
RW
RW
RW
RO
RW
RW
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