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M16C/62P Group (M16C/62P, M16C/62PT)
15.2 Timer B
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TB1IN pin of Timer
B1.
[Precautions when using Timer B1]
• Event Counter Mode
• Pulse Period/Pulse Width Measurement Mode
Figure 15.15 shows a block diagram of Timer B. Figures 15.16 and 15.17 show registers related to Timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0
to 5) to select the desired mode.
• Timer Mode: The timer counts an internal count source.
• Event Counter Mode: The timer counts pulses from an external device or overflows or underflows of
• Pulse Period/Pulse Width Measurement Mode: The timer measures pulse period or pulse width of an
Select Clock Source
TCK1 to TCK0
00
f1 or f2
01
f8
10
f32
11
fC32
TBj Overflow
(Note 1, 2)
Polarity Switching
TBiIN
and Edge Pulse
i=0 to 5
NOTES:
1. Overflows or underflows.
2. j=i-1, except j=2 when i=0 j=5 when i=3
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register
TBiS : Bits in the TABSR and the TBSR register
Figure 15.15 Timer B Block Diagram
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
The external input signals cannot be counted. Set the TCK1 bit in the
TB1MR register to "1" when using the Event Counter Mode.
This mode cannot be used.
other timers.
00: Timer
10: Pulse Period and Pulse
Width Measurement
TCK1
1
01:
Event Counter
0
page 137
f o
3
6
4
external signal.
TMOD1 to TMOD0
TBiS
Counter Reset Circuit
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
15. Timers
High-order Bits of Data Bus
Low-order Bits of Data Bus
8 high-
8 low-order
order
bits
bits
Reload Register
Counter
Address
TBj
0391h
0390h
Timer B2
-
0393h
0392h
Timer B0
-
0395h
0394h
Timer B1
-
0351h
0350h
Timer B5
-
0353h
0352h
Timer B3
-
0355h
0354h
Timer B4
-
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