Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
fAD
ADTRG
VREF
AVSS
PM00
(1)
PM01
Port P0 group
AN0_0
AN0_1
AN0_2
AN0_3
AN0_4
AN0_5
AN0_6
AN0_7
Port P2 group
AN2_0
AN2_1
AN2_2
AN2_3
AN2_4
AN2_5
AN2_6
AN2_7
ANEX0
ANEX1
NOTES :
1. Port P0 group (AN0_0 to AN0_7) can be used as analog input pins even when PM01 to PM00 bits
are set to "01b" (memory expansion mode) and PM05 to PM04 bits are set to "11b" (multiplex bus
allocated to the entire CS space).
Figure 18.1 A/D Converter Block Diagram
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
CKS2
0
1
1/3
TRG
0
Software trigger
1
0
Resistor ladder
1
VCUT
Successive conversion register
AD0 register (16)
AD1 register (16)
AD2 register (16)
AD3 register (16)
AD4 register (16)
AD5 register (16)
AD6 register (16)
AD7 register (16)
Data bus high-order
Data bus low-order
Port P10 group
CH2 to CH0
=000b
=001b
=010b
=011b
=100b
=101b
=110b
=111b
CH2 to CH0
=000b
=001b
=010b
=011b
=100b
=101b
=110b
ADGSEL1 to ADGSEL0=10b
=111b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=11b
OPA1 to OPA0=11b
OPA0=1
OPA1=1
page 208
f o
3
6
4
A/D conversion rate selection
1/2
1/2
A/D trigger
ADCON1 register
ADCON0 register
Decoder
for A/D register
ADCON2 register
CH2 to CH0
=000b
AN0
=001b
AN1
=010b
AN2
=011b
AN3
=100b
AN4
=101b
AN5
=110b
AN6
=111b
AN7
ADGSEL1 to ADGSEL0=00b
OPA1 to OPA0=11b
PM01 to PM00=00b
OPA1 to OPA0=11b
18. A/D Converter
CKS1
1
1
0
0
CKS
V
ref
Decoder
for channel
selection
VIN
ADGSEL1 to ADGSEL0=00b
OPA1 to OPA0=00b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=10b
OPA1 to OPA0=00b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=11b
OPA1 to OPA0=00b
OPA1 to OPA0
=01b
OPA1=1
ø
AD
Comparator
Advertisement
Table of Contents
