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M16C/62P Group (M16C/62P, M16C/62PT)
Transfer clock
UiC1 register
"1"
TE bit
"0"
UiC1 register
TI bit
"1"
"0"
"H"
CTSi
"L"
TXDi
UiC0 register
"1"
TXEPT bit
"0"
"1"
SiTIC register
IR bit
"0"
The above timing diagram applies to the case where the register bits are set
as follows:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• CRD bit in UiC0 register = 0 (CTS/RTS enabled) and CRS bit = 0 (CTS selected)
• UiIRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
Transfer clock
"1"
UiC1 register
TE bit
"0"
"1"
UiC1 register
TI bit
"0"
TXDi
"1"
UiC0 register
TXEPT bit
"0"
"1"
SiTIC register
IR bit
"0"
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
The transfer clock stops momentarily as CTSi is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to "L".
TC
Write data to the UiTB register
Start
bit
ST
D0 D1 D2 D3 D4 D5 D6 D7
TC
Write data to the UiTB register
Start
bit
ST
D0 D1 D2 D3 D4 D5 D6 D7
page 175
f o
3
6
4
Transferred from UiTB register to UARTi transmit register
Parity
Stop
bit
bit
P
SP
ST
D0 D1 D2 D3 D4 D5 D6 D7
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
Transferred from UiTB register to UARTi
transmit register
Stop
Stop
bit
bit
D8
SP
SP
ST
D0 D1 D2 D3 D4 D5 D6 D7
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
ocste
ocsteCT C.0001 Tc-0.0iTB r2001 TD.RmB r2 -1.iTIC register
IR bit
17. Serial I/O
Stopped pulsing
because the TE bit = 0
ST
D0 D1
P SP
D8
SPSP
ST
D0 D1
Write data to the UiTB
registerWrite d25 80 Twc6o
IR bit
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