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M16C/62P Group (M16C/62P, M16C/62PT)
Table 22.5 Status Register
Bit in
Bits in
FMR0
Status
Register
Register
SR7 (D7)
FMR00
SR6 (D6)
SR5 (D5)
FMR07
SR4 (D4)
FMR06
SR3 (D3)
SR2 (D2)
SR1 (D1)
SR0 (D0)
• D0 to D7: These data buses are read when the read status register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to "0" by executing the clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to "1," the program, block erase, erase all unlocked
block and lock bit program commands are not accepted.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Status Name
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
page 262
f o
3
6
4
Definition
"0"
Busy
-
Terminated normally
Terminated normally
-
-
-
-
22. Flash Memory Version
Value
"1"
Reset
Ready
-
Terminated in error
Terminated in error
-
-
-
-
after
1
0
0
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