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M16C/62P Group (M16C/62P, M16C/62PT)
Priority level of each interrupt
INT1
Timer B2
Timer B0
Timer A3
Timer A1
Timer B4, UART1 bus collision
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer B3, UART0 bus collision
Timer B5
UART1 reception, ACK1
UART0 reception, ACK0
UART2 reception, ACK2
A/D conversion
DMA1
UART 2 bus collision
SI/O4, INT5
Timer A0
UART1 transmission, NACK1
UART0 transmission, NACK0
UART2 transmission, NACK2
Key input interrupt
DMA0
SI/O3, INT4
IPL
I flag
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Voltage down detection
DBC
NMI
Figure 12.9 Interrupts Priority Select Circuit
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Level 0 (initial value)
f o
3
6
4
page 102
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Interrupt request level resolution output to clock
generating circuit (Fig10.1 Clock Generation Circuit)
12. Interrupt
Interrupt request
accepted
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