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M16C/62P Group (M16C/62P, M16C/62PT)
UARTi Special Mode Register 4 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Set to "0" when each condition is generated.
Figure 17.10 U0SMR4 to U2SMR4 Registers
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Symbol
U0SMR4 to U2SMR4
Bit
Bit Name
Symbol
Start Condition
STAREQ
Generate Bit
Restart Condition
RSTAREQ
Generate Bit
Stop Condition
STPREQ
Generate Bit
STSPSEL
SCL,SDA Output
Select Bit
ACKD
ACK Data Bit
ACK Data Output
ACKC
Enable Bit
SCL Output Stop
SCLHI
Enable Bit
SCL Wait Bit 3
SWC9
page 163
f o
3
6
4
Address
036Ch, 0370h, 0374h
0 : Clear
(1)
1 : Start
0 : Clear
(1)
1 : Start
0 : Clear
(1)
1 : Start
0 : Start and stop conditions not output
1 : Start and stop conditions output
0 : ACK
1 : NACK
0 : Serial I/O data output
1 : ACK data output
0 : Disabled
1 : Enabled
0 : SCL "L" hold disabled
1 : SCL "L" hold enabled
After Reset
00h
Function
17. Serial I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
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