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M16C/62P Group (M16C/62P, M16C/62PT)
12.5.4 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 12.4 shows time required for
executing the interrupt sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading ad-
dress 000000h. Then, the IR bit applicable to the interrupt information is set to "0" (interrupt re-
quested).
(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register
(3) The I, D and U flags in the FLG register become as follows:
• The I flag is set to "0" (interrupt disabled)
• The D flag is set to "0" (single-step interrupt disabled)
• The U flag is set to "0" (ISP selected)
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The temporary register within the CPU is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt in IPL is set.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the
interrupt routine.
NOTES:
1. Temporary register cannot be modified by users.
1
CPU clock
Address bus
Data bus
RD
WR
(2)
NOTES :
1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
2. The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Figure 12.4 Time Required for Executing Interrupt Sequence
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
2
3
4
5
Address
Indeterminate
0000h
Interrupt
Indeterminate
information
Indeterminate
page 97
f o
3
6
4
6
7
8
9
10
(1)
SP-2
SP-2
(1)
contents
(1)
(1)
11
12
13
14
15
SP-4
vec
vec+2
SP-4
vec
vec+2
contents
contents
contents
12. Interrupt
within the CPU.
16
17
18
PC
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