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M16C/62P Group (M16C/62P, M16C/62PT)
2
Table 17.13 I
C Mode Functions
Function
Factor of Interrupt Number
(1, 5, 7)
6, 7 and 10
Factor of Interrupt Number
(1, 6)
15, 17 and 19
Factor of Interrupt Number
(1, 6)
16, 18 and 20
Timing for Transferring
Data From the UART
Reception Shift Register to
the UiRB Register
UARTi Transmission
Output Delay
Functions of P6_3, P6_7
and P7_0 Pins
Functions of P6_2, P6_6
and P7_1 Pins
Functions of P6_1, P6_5
and P7_2 Pins
Noise Filter Width
Read RXDi and SCLi Pin
Levels
Initial Value of TXDi and
SDAi Outputs
Initial and End Values of
SCLi
(6)
DMA1 Factor
Store Received Data
Read Received Data
i = 0 to 2
NOTES :
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to "1" (interrupt requested). (Refer to 24.6 Precautions for Interrupts)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to "0" (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial I/O disabled).
3. Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
4. First data transfer to UiRB register (Falling edge of SCLi 9th bit)
5. See Figure 17.24 STSPSEL Bit Functions.
6. See Figure 17.22 Transfer to UiRB Register and Interrupt Timing.
7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to "1" (factor of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR27 bit to "1" (factor of interrupt: UART1 bus collision).
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Clock Synchronous Serial I/O
Mode (SMD2 to SMD0 = 001b,
IICM = 0)
UARTi transmission
Transmission started or
completed (selected by UiIRS)
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
TXDi output
RXDi input
CLKi input or output selected
15ns
Possible when the
corresponding port direction bit
= 0
CKPOL = 0 (H)
CKPOL = 1 (L)
UARTi reception
1st to 8th bits of the received
data are stored into bits 7 to 0
in the UiRB register
The UiRB register status is read
page 184
f o
3
6
4
2
I
C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
CKPH = 0
CKPH = 1
(No clock delay)
(Clock delay)
Start condition detection or stop condition detection
(See Table 17.14 STSPSEL Bit Functions)
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
Acknowledgment detection
(ACK)
Rising edge of SCLi 9th bit
Rising edge of SCLi 9th bit
Delayed
SDAi input/output
SCLi input/output
(Cannot be used in I
200ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I
H
L
Acknowledgment detection
(ACK)
1st to 8th bits of the received
data are stored into bits 7 to 0
in the UiRB register
17. Serial I/O
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 1
CKPH = 0
(Clock delay)
(No clock delay)
UARTi transmission
UARTi transmission
Falling edge of SCLi
Rising edge of
next to the 9th bit
SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Falling edge of
Falling and rising
SCLi 9th bit
edges of SCLi 9th
bit
2
C mode)
2
(2)
C mode
H
L
UARTi reception
Falling edge of SCLi 9th bit
1st to 7th bits of the received data are
stored into bits 6 to 0 in the UiRB
register. 8th bit is stored into bit 8 in the
UiRB register.
1st to 8th bits are stored
into bits 7 to 0 in the
UiRB register
Bits 6 to 0 in the UiRB
(4)
register
are read as
bits 7 to 1. Bit 8 in the
UiRB register is read as
bit 0.
(3)
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