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M16C/62P Group (M16C/62P, M16C/62PT)
CM10=1(stop mode)
WAIT instruction
RESET
Software reset
NMI
Interrupt request level judgment output
CM02, CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
PCLK0, PCLK1: Bits in PCLKR register
CM21, CM27
: Bits in CM2 register
Oscillation Stop, Re-Oscillation Detection Circuit
Main
clock
PLL Frequency Synthesizer
Main clock
Figure 10.1 Clock Generation Circuit
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Sub-clock
generating circuit
XCIN
XCOUT
CM04
CM21
S
Q
XIN
XOUT
R
Main
clock
Main clock
generating circuit
CM05
S
Q
R
Pulse generation
Charge,
circuit for clock
discharge
edge detection
circuit
and charge,
discharge control
Programmable
counter
Phase
comparator
page 66
f o
3
6
4
I/O ports
PM01–PM00=00b, CM01–CM00=01b
PM01–PM00=00b, CM01–CM00=10b
Sub-clock
fC
On-chip
On-chip
oscillator
oscillator
clock
Oscillation
stop, re-
oscillation
detection
circuit
PLL
frequency
synthesizer
PLL
CM21=1
clock
1
0
CM21=0
CM11
CM02
e
1/2
1/2
a
1/2
CM06=0
CM17–CM16=01b
CM06=0
CM17–CM16=00b
Reset
CM27=0
generating
Oscillation stop
circuit
detection reset
Oscillation stop,
re-oscillation
CM27=1
detection interrupt
generating circuit
CM21 switch signal
Voltage
Charge
control
pump
oscillator
(VCO)
Internal low-
pass filter
10. Clock Generating Circuit
CM01–CM00=00b
PM01–PM00=00b,
CM01–CM00=11b
fC32
1/32
f1
PCLK0=1
f2
PCLK0=0
f8
f32
fAD
f1SIO
PCLK1=1
f2SIO
PCLK1=0
f8SIO
f32SIO
c
e
b
a
CM07
0
d
=
Divider
fC
CM07
1
=
b
1/2
1/2
1/2
1/4
1/8
1/16
CM06=0
CM17–CM16=11b
CM06=1
CM06=0
CM17–CM16=10b
Details of divider
Oscillation stop,
re-oscillation
detection signal
1/2
PLL clock
CLKOUT
D4INT clock
CPU clock
BCLK
c
1/32
d
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