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M16C/62P Group (M16C/62P, M16C/62PT)
• Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit)
UiBRG count
source
UiC1 register
RE bit
RXDi
Transfer clock
UiC1 register
RI bit
RTSi
SiRIC register
IR bit
The above timing diagram applies to the case where the register bits are set as follows:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 17.16 Receive Operation
17.1.2.1 Bit Rates
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 17.9 lists example of bit rates and settings.
Table 17.9 Example of Bit Rates and Settings
B
t i
R
a
e t
C
o
u
b (
p
) s
1
2
0
0
2
4
0
0
4
8
0
0
9
6
0
0
1
4
4
0
0
1
9
2
0
0
2
8
8
0
0
3
1
2
5
0
3
8
4
0
0
5
1
2
0
0
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
"1"
"0"
Start bit
Sampled "L"
Reception triggered when transfer clock
"1"
is generated by falling edge of start bit
"0"
"H"
"L"
"1"
"0"
P
r e
p i
h
r e
l a
t n
S
o
u
c r
e
f o
B
R
G
S
t e
V
a
u l
e
f o
8 f
1
8 f
8 f
1 f
1
1 f
1 f
1 f
1 f
1 f
1 f
page 176
f o
3
6
4
D0
D1
Receive data taken in
Transferred from UARTi receive
register to UiRB register
Set to "0" by an interrupt request acknowledgement or by program
F
u
n
t c
o i
n
C
o l
k c
:
1
6
M
H
z
B
R
G
:
n
A
c
u t
l a
i T
m
e
b (
p
) s
0
3
6 (
7
) h
1
2
0
5
1
3 (
3
) h
2
4
0
2
5
1 (
9
) h
4
8
0
0
3
6 (
7
) h
9
6
1
6
8
4 (
4
) h
1
4
4
9
5
1
3 (
3
) h
1
9
2
3
4
2 (
2
) h
2
8
5
3
1
1 (
F
) h
3
1
2
5
2
5
1 (
9
) h
3
8
4
6
1
9
1 (
3
) h
5
0
0
0
Stop bit
D7
P
r e
p i
h
r e
l a
F
u
n
t c
o i
n
S
t e
v
a
u l
e
f o
B
R
G
:
n
2
1
5
5
9 (
6
) h
4
7
7
4 (
6
) h
8
3
8
2 (
6
) h
5
1
5
5
9 (
6
) h
3
1
0
3
6 (
7
) h
3
1
7
7
4 (
6
) h
7
1
5
1
3 (
3
) h
0
4
7
2 (
F
) h
2
3
8
2 (
6
) h
0
2
8
1 (
C
) h
17. Serial I/O
C
o l
k c
:
2
4
M
H
z
A
c
u t
l a
i T
m
e
b (
p
) s
1
2
0
2
2
4
0
4
4
8
0
8
9
6
1
5
1
4
4
2
3
1
9
2
3
1
2
8
8
4
6
3
1
2
5
0
3
8
4
6
2
5
1
7
2
4
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