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M16C/62P Group (M16C/62P, M16C/62PT)
System Clock Control Register 1
b7
b6
b5
b4
b3
b2
b1
0 0
0
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. When entering stop mode from high or middle speed mode, or when the CM05 bit is set to "1" (main clock turned off) in low
speed mode, the CM15 bit is set to "1" (drive capability high).
3. Effective when the CM06 bit is "0" (CM16 and CM17 bits enable).
4. If the CM10 bit is "1" (stop mode), XOUT goes "H" and the internal feedback resistor is disconnected. The XCIN and XCOUT
pins are placed in the high-impedance state. When the CM11 bit is set to "1" (PLL clock), or the CM20 bit in the CM2 register is
set to "1" (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to "1".
5. After setting the PLC07 bit in the PLC0 register to "1" (PLL operation), wait until Tsu (PLL) elapses before setting the CM11 bit to
"1" (PLL clock).
6. When the PM21 bit in the PM2 register is set to "1" (clock modification disable), writing to the CM10, CM11 bits has no effect.
When the PM22 bit in the PM2 register is set to "1" (watchdog timer count source is on-chip oscillator clock), writing to the CM10
bit has no effect.
7. Effective when CM07 bit is "0" and CM21 bit is "0" .
Figure 10.3 CM1 Register
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
(1)
b0
Symbol
CM1
Bit Symbol
Bit
Name
All Clock Stop Control Bit
CM10
(4, 6)
System Clock Select Bit 1
CM11
(6, 7)
Reserved Bit
(b4-b2)
XIN-XOUT Drive Capacity
CM15
(2)
Select Bit
Main Clock Division
CM16
(3)
Select Bit 1
CM17
page 68
f o
3
6
4
Address
After Reset
0007h
00100000b
0 : Clock on
1 : All clocks off (stop mode)
0 : Main clock
(5)
1 : PLL clock
"0"
Set to
0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
10. Clock Generating Circuit
Function
RW
RW
RW
RW
RW
RW
RW
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