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M16C/62P Group (M16C/62P, M16C/62PT)
Main clock, PLL clock, or on-chip oscillator clock
(UART2)
RXD2
Clock source selection
CLK1 to CLK0
00
f1SIO or f2SIO
01
f8SIO
10
f32SIO
CKPOL
polarity
CLK2
reversing
circuit
CTS/RTS selected
CTS2 /
RTS2
CRS
n2: Values set to the U2BRG register
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in U2MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
NOTES :
1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Figure 17.3 UART2 Block Diagram
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
RXD polarity reversing
circuit
1/16
CKDIR
Internal
U2BRG
register
0
1 / (n2+1)
1/16
1
External
1/2
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLK
CTS/RTS disabled
1
VSS
CTS/RTS disabled
0
1
0
CRD
page 156
f o
3
6
4
PCLK1
f2SIO
0
1/2
1/2
f1SIO
1
1/8
1/4
UART reception
SMD2 to SMD0
010, 100, 101, 110
Reception
Clock synchronous
control circuit
type
001
UART transmission
010, 100, 101, 110
Transmission
control circuit
Clock synchronous
type
001
Clock synchronous type
(when internal clock is selected)
0
1
CKDIR
RTS2
CTS2
17. Serial I/O
f1SIO or f2SIO
f8SIO
f32SIO
TXD
polarity
reversing
Transmit/
circuit
receive
Receive
unit
clock
Transmit
clock
TXD2
(1)
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