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M16C/62P Group (M16C/62P, M16C/62PT)
(1) Transmission
Transfer clock
"1"
U2C1 register
TE bit
"0"
"1"
U2C1 register
TI bit
"0"
TXD2
Parity error signal sent
back from receiving end
(1)
RXD2 pin level
"1"
U2C0 register
TXEPT bit
"0"
"1"
S2TIC register
IR bit
"0"
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
NOTES:
1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of the TXD2 output and parity error signal
sent back from receiving end, is generated.
(1) Reception
Transfer clock
"1"
U2C1 register
RE bit
"0"
Transmit waveform from
the transmitting end
TXD2
(1)
RXD2 pin level
U2C0 register
"1"
RI bit
"0"
S2RIC register
"1"
IR bit
"0"
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
NOTES:
1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of transmit waveform from the transmitting end
and parity error signal from receiving end, is generated.
Figure 17.30 Transmit and Receive Timing in SIM Mode
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Tc
Start
bit
ST
D0 D1 D2 D3 D4 D5 D6 D7
ST
D0 D1 D2 D3 D4 D5 D6 D7
The IR bit is set to "1" at the
falling edge of transfer clock
Tc
Start
bit
ST
D0 D1 D2 D3 D4 D5 D6 D7
ST
D0 D1 D2 D3 D4 D5 D6 D7
page 199
f o
3
6
4
Write data to U2TB register
Transferred from U2TB register to UART2 transmit register
Parity
Stop
bit
bit
ST
D0 D1 D2 D3 D4 D5 D6 D7
P
SP
An "L" level returns due to the
occurrence of a parity error.
P
SP
ST
D0 D1 D2 D3 D4 D5 D6 D7
The level is detected by the
interrupt routine.
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Stop
Parity
bit
bit
P
SP
ST
D0 D1 D2 D3 D4 D5 D6 D7
An "L" level is output from TXD2 due to
the occurrence of a parity error
P
SP
ST
D0 D1 D2 D3 D4 D5 D6 D7
Read the U2RB register
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
17. Serial I/O
P
SP
P
SP
The level is
detected by the
interrupt routine.
SP
P
P
SP
Read the U2RB register
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