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M16C/62P Group (M16C/62P, M16C/62PT)
UART Transmit/Receive Control Register 2
b7
b6
b5
b4
b3
b2
NOTES :
1. When using multiple transfer clock output pins, make sure the following conditions are met:
CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
NOTES:
1. The BBS bit is set to "0" by writing "0" in a program. (Writing "1" has no effect)
2. Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
3. When a transfer begins, the SSS bit is set to "0" (Not synchronized to RXDi).
Figure 17.8 UCON Register and U0SMR to U2SMR Registers
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
b1
b0
Symbol
UCON
Bit
Bit Name
Symbol
U0IRS
UART0 Transmit Interrupt
Cause Select Bit
U1IRS
UART1 Transmit Interrupt
Cause Select Bit
U0RRM
UART0 Continuous
Receive Mode Enable Bit
U1RRM
UART1 Continuous
Receive Mode Enable Bit
CLKMD0
UART1 CLK/CLKS
Select Bit 0
CLKMD1
UART1 CLK/CLKS
(1)
Select Bit 1
Separate UART0
RCSP
CTS/RTS Bit
Nothing is assigned. When write, set "0". When read, its content is indeterminate.
(b7)
Symbol
U0SMR to U2SMR
Bit
Bit Name
Symbol
2
I
C Mode Select Bit
IICM
ABC
Arbitration Lost Detecting
Flag Control Bit
Bus Busy Flag
BBS
Reserved Bit
(b3)
Bus Collision Detect
ABSCS
Sampling Clock Select Bit
ACSE
Auto Clear Function
Select Bit of Transmit
Enable Bit
Transmit Start Condition
SSS
Select Bit
Nothing is assigned. When write, set "0". When read, its content is indeterminate.
(b7)
page 161
f o
3
6
4
Address
After Reset
03B0h
X0000000b
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Effective when CLKMD1 = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS0 supplied from the P6_4 pin)
Address
After Reset
036Fh, 0373h, 0377h
X0000000b
2
0 : Other than I
C mode
2
1 : I
C mode
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
Set to "0"
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
0 : Not synchronized to RXDi
1 : Synchronized to RXDi
Function
Function
(2)
(3)
17. Serial I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(1)
RW
RW
RW
RW
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