Renesas M16C/62P Hardware Manual page 210

M16C/62P Group (M16C/62P, M16C/62PT)
(1) The ABSCS Bit in the UiSMR Register (Bus collision detect sampling clock select)
Transfer clock
TXDi
RXDi
Timer Aj
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
(2) The ACSE Bit in the UiSMR Register (Auto clear of transmit enable bit)
Transfer clock
TXDi
RXDi
UiBCNIC register
(1)
IR bit
UiC1 register
TE bit
NOTES :
1. BCNIC register when UART2.
(3) The SSS Bit in the UiSMR Register (Transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TXDi
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge
CLKi
TXDi
RXDi
NOTES :
1. The falling edge of RXDi when IOPOL=0; the rising edge of RXDi when IOPOL =1.
2. The transmit condition must be met before the falling edge
This diagram applies to the case where IOPOL=1 (reversed).
Figure 17.29 Bus Collision Detect Function-Related Bits
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
ST D0
Input to TAjIN
ST D0
ST D0
ST D0
(NOTE 2)
page 196
f o 3 6 4
D1 D2 D3 D4
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
D1 D2 D3 D4
D1 D2 D3 D4
(1)
of RXDi
D1 D2 D3 D4
(1)
of RXD.
D5 D6 D7 D8
D5 D6 D7 D8
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to "0"
(transmission disabled) when the
IR bit in the UiBCNIC register= 1
(unmatching detected).
D5 D6 D7 D8
D5 D6 D7 D8
17. Serial I/O
(i=0 to 2)
SP
SP
SP
SP