Each Register Of Ei Os Descriptor (Isd); Fig. 6.14 Configuration Of Data Counter (Dct); Fig. 6.15 Configuration Of I/O Register Address Pointer (Ioa) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F
6.6.2 Each Register of EI
2
The EI OS descriptor (ISD) consists of the following registers.
• Data counter (DCT)
• I/O Register address pointer (IOA)
• EI
2
OS status register (ISCS)
• Buffer address pointer (BAP)
Note that the initial value of each register is undefined at a reset.
n Data counter (DCT)
The data counter (DCT) is an 16-bit length register and a counter corresponding to the count of the data to
be transferred. After data transfer, the counter is decremented by one. When the value of this counter
2
becomes zero, EI OS terminates. Figure 6.14 shows the configuration of DCT.
bit 15 bit 14 bit 13
DCT B15 B14 B13
R/W R/W R/W
R/W : Both read and write
X : Undefined
n I/O register address pointer (IOA)
The I/O register address pointer (IOA) is a 16-bit length register to transfer data with the buffer. The register
indicates the lower addresses (A15 to A0) of the I/O register. The upper addresses (A23 to A16) are all 0s.
This register can be used to specify any I/O register at addresses 000000
the configuration of IOA.
bit 15 bit 14 bit 13 bit 12
IOA A15 A14 A13
R/W R/W R/W
R/W : Both read and write
X : Undefined

Fig. 6.15 Configuration of I/O Register Address Pointer (IOA)

2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
2
OS Descriptor (ISD)
DCTH
bit 12 bit 11 bit 10 bit 9 bit 8
B12 B11 B10 B09 B08
R/W R/W R/W R/W R/W

Fig. 6.14 Configuration of Data Counter (DCT)

IOAH
bit 11 bit 10 bit 9 bit 8
A12 A11 A10 A09 A08
R/W R/W R/W R/W R/W
DCTL
bit 7 bit 6 bit 5 bit 4 bit 3
B05
B07 B06 B04 B03
R/W R/W R/W R/W R/W
IOAL
bit 7 bit 6 bit 5 bit 4 bit 3
A05
A07 A06 A04 A03
R/W R/W R/W R/W R/W
6-26
Initial value
bit 2 bit 1 bit 0
B02 B01 B00 XXXXXXXXXXXXXXXX
R/W R/W R/W
to 00FFFF . Figure 6.15 shows
H H
Initial value
bit 2 bit 1 bit 0
A02 A01 A00 XXXXXXXXXXXXXXXX
R/W R/W R/W
B
B