Gtx Tx Reset In Response To Completion Of Configuration; Gtx Tx Reset In Response To Gtxtxreset Pulse - Xilinx Virtex-6 FPGA User Manual

GTX TX Reset in Response to Completion of Configuration

Figure 3-10
powered-up GTX transceiver. The same sequence is activated any time
TXPLLPOWERDOWN goes from High to Low during normal operation.
X-Ref Target - Figure 3-10
TXRESETDONE
Notes relevant to
1.
2.

GTX TX Reset in Response to GTXTXRESET Pulse

Figure
GTXTXRESET. GTXTXRESET acts as an asynchronous reset signal. The guideline for the
asynchronous GTXTXRESET pulse width is one period of the reference clock.
X-Ref Target - Figure 3-11
TXRESETDONE
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
shows the GTX TX reset following the completion of configuration of a
GSR
TX Reset FSM Wait
TXPLLLKDET/
RXPLLLKDET
GTXTEST[1]
Figure 3-10: Transmitter Reset After Configuration
Figure 3-10:
GTXTEST[1] is only required when the TX output clock divider,
TXPLL_DIVSEL_OUT, is set to /2 or /4.
The timing of the reset sequencer inside the GTX TX depends on the frequency of an
internal clock and certain configuration attributes. The estimate given in
assumes that the frequency of the internal clock is 50 MHz with default values for the
configuration attributes.
3-11, similar to Figure
GTXTXRESET
TX Reset FSM Idle Wait
TXPLLLKDET/
RXPLLLKDET
GTXTEST[1]
Figure 3-11: Transmitter Reset After GTXTXRESET Pulse
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~120 µs
Reset in Progress
1024
(1) CLKs
3-10, shows the reset occurring in response to a pulse on
~120 µs
Reset in Progress
1024
(1) CLKs
TX Initialization
IDLE
256 256 256
CLKs CLKs CLKs
UG366_c3_28_092710
Figure 3-10
Idle
256 256 256
CLKs CLKs CLKs
UG366_c3_29_092710
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