Pcb Technology And Stackup; Pcb Technology Considerations; Figure 3. System Diagram - Intel Quark D2000 Design Manual

System Assumptions

Figure 3. System Diagram

2.1.1

PCB Technology and Stackup

The system uses the PCB technology of a standard interconnect, Type 3, 4-layer board,
no blind or buried vias. It is important to note that variations in the stackup of a
motherboard, such as changes in the dielectric height, trace widths, and spacing, can
impact the impedance, loss, and jitter characteristics of all the interfaces. Such changes
may be intentional, or may be the result of variations in the manufacturing process. In
either case, they must be properly considered when designing interconnects. This
design guide applies the CRB PCB stackup and trace width/spacing that is shown in
Figure 4.
All the routing guidelines in this document are simulated based on the CRB stackup.
Note:
2.1.2

PCB Technology Considerations

The typical values, including the design and material tolerances, are centered on a
nominal single line impedance specification of 50�� ± 15% for microstrip. Many
interfaces specify a different nominal single-ended impedance. For more details on the
November 2016
Document Number: 333580-002EN
Intel® Quark™ Microcontroller D2000
Platform Design Guide
11