Pcb Technology And Stackup; Pcb Technology Considerations; Figure 2. Soc Block Diagram - Intel Quark SE Series Platform Manual

System Assumptions

Figure 2. SoC Block Diagram

System Control SubSystem
Wake Event
Routing
Interrupt
Routing
System Control
Interface & Registers
JTAG/TAP/
DFx Test
Controller(s)
PERIPH
JTAG
2.1.1

PCB Technology and Stackup

The system uses the PCB technology of a standard interconnect, Type 3, 6-layer
board, with no blind or buried vias. The BGA package also supports a standard
interconnect, Type 3, 4-layer PCB design technology. It is important to note that
variations in the stackup of a motherboard, such as changes in the dielectric height,
trace widths, and spacing, can impact the impedance or loss and jitter
characteristics of all interfaces. Such changes may be intentional or may be a result
of variations in the manufacturing process. In either case, they must be properly
considered when designing interconnects. This design guide applies the CRB PCB
stackup and trace width/spacing that is shown in
All routing guidelines in this document are simulated based on the CRB stackup.
Note:
2.1.2

PCB Technology Considerations

The typical values, including the design and material tolerances, are centered on a
nominal single line impedance specification of 50�� ± 15% for microstrip. Many
interfaces specify a different nominal single-ended impedance. For more details on
the nominal trace width to meet those impedance targets, refer to the individual
interface section.
Follow these general stackup recommendations:
 Microstrip layers are assumed to be built from 1/2oz. foil, plated up nominally
another 1 oz. However, the defined trace thickness range allows for significant
process variance around this nominal.
 Dual stripline is assumed to be built from 1 oz. copper, based on the Intel®
Quark™ SE Microcontroller C1000 layout layers 2/3/4/5.
June 2017
Document Number: 334715-004EN
Host Processor
VRs/
LDOs
OSC Processor
PMU
Core
PLL
CRU
AHB Bridge
Multi-Channel
DMA
Controller
WDT RTC
APB Fabric
I2C (2 Master & SPI (2 Master & 1
GPIO
1 Slave) Slave)
Digital I/O Pads
SRAM
80kB
Local APIC
I/O APIC
Interrupts
192kBx2
AHB Fabric
Pattern Matching
I2S + Fifo PWM
2 x UART
Memories (Timer)
Pin Muxing
Comparator HIPs
Figure
Intel® Quark™ SE Microcontroller C1000
OTP
Flash
Flash
USB 1.1 Device
Controller
Sensor Processor Subsystem
ARC DSP
DCCM
Memory Core
Interrupts
Engine
I2C SPI GPIO
Analog I/O Pads
3.
Platform Design Guide
ADC
Controller
SAR ADC
11