Fpga Configuration; Fpga Programming Over Embedded Usb-Blaster - Intel Stratix 10 GX User Manual

4 Board Components
Figure 4. I2C Block Diagram
Intel
Stratix 10
MAX V
MAX II USB
USB-PHY

4.4 FPGA Configuration

This section describes the FPGA, flash memory and MAX V CPLD System Controller
device programming methods supported by the Intel Stratix 10 GX tranceiver signal
integrity development kit.
Three configuration methods except AS mode are mostly used on the Intel Stratix 10
transceiver signal integrity development kit.
• Embedded USB-Blaster is the default method for configuring the FPGA at any time
using the Intel Quartus Prime Programmer in JTAG mode with the supplied USB
cable.
• MAX V configures the FPGA device via AvST mode using stored images from CFI
flash devices either at power-up or pressing the
button.
• JTAG external header for debugging. Intel recommends that you use lower JTAG
clock frequency value such as 16 MHz.

4.4.1 FPGA Programming over Embedded USB-Blaster

Embedded USB-Blaster is the default method for configuring the Intel Stratix 10 GX
FPGA using the Intel Quartus Prime Programmer in the JTAG mode with the supplied
USB cable.
net name = I2C_1V8_SCL
S1
U43
(1.8 to 2.5 V)
I C Buffer
U20 2
U26
U97
(1.8 to 5 V)
I C Buffer
2
U9
U28
(1.8 to 3.3 V)
I C Buffer
2
net name = I2C_3V3_SCL
U27
(1.8 to 3.3 V)
I C Buffer
2
U29
®
Intel Stratix
add = 74h add = 76h
Si5341 Si5341
PLL PLL
(1.8 V) (1.8 V)
net name = I2C_1V8_SCL_Si5341
add = 66h add = 77h
Si570 OSC Si570 OSC
(2.5 V) (2.5 V)
net name = I2C_2V5_SCL
add = 66h
Si570 OSC
(2.5 V)
net name = I2C_5V_SCL
add = 5Bh
add = 5Eh add = 18h add = 5C/5Dh
MAX 10 MAX 1619 LTM2987
FPGA PM0/1
SW2
MAX_RESETn
®
10 GX Transceiver Signal Integrity Development Kit User Guide
J102 Silab
Debug Cable
add = 31h/5Ah
add = 4Fh
LTM4677
J17 LT
net name =LT_SCL Debug Cable
/ push
PGM_CONFIG
23