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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
14. A/D Converter
Note
P9
and P9
(AN
2
3
Do not use P9
and P9
2
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10
AN
), P9
to P9
(AN3
7
0
3
using these inputs, make sure the corresponding port direction bits are set to "0" (input mode).
When not using the A/D converter, set the VCUT bit to "0" (V
from the V
pin into the resistor ladder, helping to reduce the power consumption of the chip.
REF
The A/D conversion result is stored in the i bits in the A/D register for AN
Table 14.1 shows the A/D converter performance. Figure 14.1 shows the A/D converter block diagram
and Figures 14.2 to 14.4 show the A/D converter associated with registers.
Table 14.1 A/D Converter Performance
Item
A/D Conversion Method
Analog Input Voltage
Operating Clock fAD
Resolution
Integral Nonlinearity Error When AV
Operating Modes
Analog Input Pins
Conversion Speed Per Pin
NOTES:
1. Not dependent on use of sample and hold function.
2. Set the φAD frequency to 10 MHz or less. For M16C/26B, set it to 12 MHz or less.
Without sample-and-hold function, set the fAD frequency to 250kH
With the sample and hold function, set the fAD frequency to 1MH
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
, AN
) are not available in the 42-pin package.
32
24
(AN
, AN
) as analog input pins in the 42-pin package.
3
32
24
to AN3
, AN2
). Similarly, AD
0
2
4
Successive approximation (capacitive coupling amplifier)
(1)
0V to AV
(V
CC
(2)
f
/divided-by-2 or f
AD
or f
/divided-by-12 or f
AD
8-bit or 10-bit (selectable)
= V
CC
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±3LSB
When AV
= V
CC
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±5LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat
sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1
(3)
8 pins (AN
to AN
0
8 pins (AN
to AN
0
• Without sample and hold function
8-bit resolution: 49 f
• With sample and hold function
8-bit resolution: 28 f
page 180
f o
3
2
9
6
C
2 /
6
) T
___________
input shares the pin with P1
TRG
REF
Performance
)
CC
/divided-by-3 or f
AD
AD
= 5V
REF
= 3.3V
REF
) + 3 pins (AN
to AN
7
30
) + 2 pins (AN
, AN
7
30
cycles, 10-bit resolution: 59 f
AD
cycles, 10-bit resolution: 33 f
AD
5
unconnected), so that no current will flow
, AN
, and AN
i
3i
/divided-by-4 or f
AD
AD
) + 1 pins (AN
) (48-pin package)
32
24
)
31
cycles
AD
cycles
AD
or more.
Z
or more.
Z
14. A/D Converter
to P10
(AN
to
0
7
0
. Therefore, when
pins (i = 0 to 7).
2i
/divided-by-6
(42-pin package)
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