Holtek HT32F12345 User Manual page 9

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Channel 1 Capture / Compare Register - CH1CCR .................................................................... 279
Channel 2 Capture / Compare Register - CH2CCR .................................................................... 280
Channel 3 Capture / Compare Register - CH3CCR .................................................................... 281
Channel 0 Asymmetric Compare Register - CH0ACR ................................................................. 282
Channel 1 Asymmetric Compare Register - CH1ACR ................................................................. 282
Channel 2 Asymmetric Compare Register - CH2ACR ................................................................. 283
Channel 3 Asymmetric Compare Register - CH3ACR ................................................................. 283
15 Basic Function Timer (BFTM) .......................................................................... 284
Introduction ........................................................................................................................ 284
Features ............................................................................................................................. 284
Functional Description ....................................................................................................... 285
Repetitive Mode ............................................................................................................................ 285
One Shot Mode ............................................................................................................................. 286
Trigger ADC Start.......................................................................................................................... 287
Register Map ..................................................................................................................... 287
Register Descriptions ......................................................................................................... 288
BFTM Control Register - BFTMCR .............................................................................................. 288
BFTM Status Register - BFTMSR ................................................................................................ 289
BFTM Counter Register - BFTMCNTR ........................................................................................ 289
BFTM Compare Value Register - BFTMCMPR ........................................................................... 290
16 Motor Control Timer (MCTM) ........................................................................... 291
Introduction ........................................................................................................................ 291
Features ............................................................................................................................. 292
Functional Descriptions ..................................................................................................... 293
Counter Mode ............................................................................................................................... 293
Clock Controller ............................................................................................................................ 296
Trigger Controller .......................................................................................................................... 297
Slave Controller ............................................................................................................................ 298
Master Controller .......................................................................................................................... 300
Channel Controller ........................................................................................................................ 301
Input Stage ................................................................................................................................... 303
Output Stage ................................................................................................................................. 304
Update Management .................................................................................................................... 313
Quadrature Decoder ..................................................................................................................... 315
Digital Filter ................................................................................................................................... 317
Clearing CHxOREF when ETIF is high ......................................................................................... 317
Single Pulse Mode ........................................................................................................................ 318
Asymmetric PWM Mode ............................................................................................................... 320
Timer Interconnection ................................................................................................................... 320
Trigger ADC Start.......................................................................................................................... 324
Lock Level Table ........................................................................................................................... 324
PDMA Request ............................................................................................................................. 325
Rev. 1.10 9 of 590 November 28, 2018