Channel Transfer; Channel Priority; Table 63. Pdma Channel Assignments - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Table 63. PDMA Channel Assignments

IP
(x = 0, 1)
CH0 CH1 CH2
ADC ADC
SPIx SPI0_RX SPI0_TX
USARTx USR0_RX
UARTx UR0_RX UR0_TX
I Cx
2
MT0_TRIG MT0_CH1
MCTMx MT0_CH0
MT1_CH0 MT1_CH2
GT0_CH1
GPTMx GT0_UEV GT0_CH2
GT0_CH3
I 2 S I2S_RX
SDIO

Channel transfer

A PDMA channel transfer is split into multiple block transactions with PDMA arbitration occurring
at the end of each block transaction. Although these channel transfers can all be activated, there
is only one block transaction being transferred through the bus at a time. The channel transfer
sequence depends upon the channel priority setting of each PDMA channel. The total transfer size
is calculated from the block transaction count and block size. The block size is equal to the product
of the block length and data bit width. For an efficient transfer, it is recommended that the block
length is set as a multiple of 4.
The total transfer data size calculation is shown as below equation:
A PDMA channel total transfer data size = Block transaction count × (Block length × Data width)

Channel Priority

The PDMA provides four priority levels, known as very high, high, medium and low, which can
be configured by the application software. The PDMA also provides two methods to determine
the channel priority. One is determined by application software configuration and the other is
determined by the fixed hardware channel number. The PDMA arbitration processor will first
check the software configuring channel priority level used to request the PDMA to provide the
data transfer services. If more than one channel has the same priority, the channel with a smaller
channel number will have priority over one with a larger channel number after arbitration.
Note that the highest priority channel will not occupy the PDMA service all the time when other
lower priority channel requests are pending. The highest priority channel will be skipped for one
block transaction time duration after one block transaction is complete. Then a block transaction
requested by the second priority channel will be performed. After a block transaction of the second
priority channel is complete, the PDMA arbitration processor will re-check all of the requested
channel priority with the exception of the second priority channel since the second priority
channel will be excluded after the end of a block transaction. Therefore, a block data transaction
of the higher priority channel will be serviced and this channel will be excluded from the priority
arbitration at the end of the block transaction. The PDMA will keep transferring the data using the
method described above until all of the requested channel data transfer is complete. Refer to the
accompanying figure for an example which shows the PDMA channel arbitration and scheduling.
Rev. 1.10
PDMA Channel Number
CH3 CH4 CH5
SPI1_RX SPI1_TX
USR0_TX
UR1_RX UR1_TX
I2C1_RX
MT0_CH3 MT0_CH2 MT0_UEV1
MT1_UEV2
MT1_UEV1 MT1_CH1 MT1_CH3
GT0_CH0
GT0_TRIG
I2S_TX
SDIO_RX
498 of 590
CH6 CH7 CH8 CH9
USR1_RX USR1_TX
I2C1_TX
MT0_UEV2
MT1_TRIG
GT1_CH1
GT1_CH0
GT1_UEV
SDIO_TX
CH10 CH11
I2C0_RX I2C0_TX
GT1_CH2
GT1_CH3
GT1_TRIG
November 28, 2018