32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Bits
Field
Descriptions
[1]
ODRXIF
OUT Data Received Interrupt Flag
This bit is set by the hardware circuitry when a data packet is successfully received
from the host for an OUT token and when an endpoint n ACK signal is sent to the
host.
Writing 1 into this status bit will clear it to 0.
[0]
OTRXIF
OUT Token Received Interrupt Flag.
This bit is set by the hardware circuitry when the endpoint receives an OUT token
from the host and is cleared to 0 by writing 1.
USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3
This register specifies the Endpoint 1 ~ 3 transfer byte count.
Offset:
0x034 (n = 1), 0x048 (n = 2), 0x05C (n = 3)
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
RW
0 RW
Bits
Field
Descriptions
[8:0]
TCNT
Transfer Byte Count
This field contains the number of bytes received by the endpoint n in the preceding
OUT transaction or the number of bytes to be transmitted by the endpoint n in the
next IN transaction.
Rev. 1.10
30
29
28
22
21
20
14
13
12
Reserved
6
5
4
0 RW
0 RW
488 of 590
27
26
Reserved
19
18
Reserved
11
10
3
2
TCNT
0 RW
0 RW
0 RW
25
24
17
16
9
8
TCNT
RW
0
1
0
0 RW
0
November 28, 2018
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