1.5 V Power Domain; Operation Modes; Table 11. Operation Mode Definitions - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

1.5 V Power Domain

The main functions that include the APB interface for the backup domain, CPU core logic, AHB
/ APB peripherals and memories and so on are located in this power domain. Once the 1.5 V is
powered up, the POR will generate a reset sequence (Refer to PORB) on 1.5 V power domain.
Subsequently, to enter the expected power saving mode, the associated control bits including
the LDOOFF, DMOSON and SLEEPDEEP bits must be configured. Then, once a WFI or WFE
instruction is executed, the device will enter an expected power saving mode which will be
discussed in the following section.

Operation Modes

Run Mode
In the Run mode, the system operates with full functions and all power domains are active. There
are two ways to reduce the power consumption in this mode. The first is to slow down the system
clock by setting the AHBPRE field in the CKCU AHBCFGR register and the second is to turn
off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down
peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application
requirement. Reducing the system clock speed before entering the sleep mode will also help to
minimize power consumption.
Additionally, there are several power saving modes to provide maximum optimization between
device performance and power consumption.

Table 11. Operation Mode Definitions

Mode name
Run
Sleep
Deep-Sleep1 ~ 2
Power-Down
Sleep Mode
By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or
SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash clock
or SRAM clock after the system enters the Sleep mode. If it is not necessary for the CPU to access
the Flash memory and SRAM in the Sleep mode, it is recommended to clear the FMCEN and
SRAMEN bits in the AHBCCR register to minimize power consumption. To enter the Sleep mode,
it is only necessary to clear the SLEEPDEEP bit to 0 and execute a WFI or WFE instruction. The
system will exit from the Sleep mode via any interrupt or event trigger. The accompanying table
provides more information about the power saving modes.
Rev. 1.10
After system reset, CPU fetches instructions to execute.
CPU clock will be stopped.
Peripherals, Flash and SRAM clocks can be stopped by setting.
Stop all clocks in the 1.5 V power domain.
Disable HSI, HSE and PLL.
Turning on the LDO low current mode or DMOS to reduce the 1.5 V power
domain current.
Shut down the 1.5 V power domain
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November 28, 2018