32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Register Descriptions
Backup Domain Status Register – BAKSR
This register indicates backup domain status.
Offset:
0x100
Reset value: 0x0000_0001 (Reset only by Backup Domain reset)
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits
Field
[8]
WUPF
[1]
PDF
[0]
BAKPORF
Rev. 1.10
30
29
28
22
21
20
14
13
12
Reserved
6
5
Reserved
Descriptions
External WAKEUP Pin Flag
0: The Wakeup pin is not asserted
1: The Wakeup pin is asserted
This bit is set by hardware when the WAKEUP pin asserts and is cleared by software
read. Software should read this bit to clear it after a system wake up from the power
saving mode.
Power Down Flag
0: Wakeup from abnormal V
1: Wakeup from Power-Down mode (Loss of V
This bit is set by hardware when the system has successfully entered the Power-
Down mode This bit is cleared by software read.
Backup Domain Reset Flag
0: Backup Domain reset does not occur
1: Backup Domain reset occurs
This bit is set by hardware when Backup Domain reset occurs, either a Backup
Domain power on reset or Backup Domain software reset. The bit is cleared by
software read. This bit must be cleared after the system is first powered, otherwise it
will be impossible to detect when a Backup Domain reset has been triggered. When
this bit is read as 1, a read software loop must be implemented until the bit returns
again to 0. This software loop is necessary to confirm that the Backup Domain is
ready for access. It must be implemented after the Backup Domain is first powered
up.
76 of 590
27
26
Reserved
19
18
Reserved
11
10
4
3
2
shutdown (Loss of V
DD15
DD15
is under expectation)
DD15
25
24
17
16
9
8
WUPF
RC
0
1
0
PDF
BAKPORF
RC
0 RC
1
is unexpected)
November 28, 2018
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