Usart Control Register - Usrcr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
USART Control Register – USRCR
The register specifies the serial parameters such as data length, parity, and stop bit for the USART. It also
contains the USART enable control bits together with the USART mode and data transfer mode selections.
Offset : 0x004
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
RTS
Type/Reset RW 0 RW
7
RXDMAEN TXDMAEN URRXEN
Type/Reset RW 0 RW
Bits Field
[15] RTS
[14] BCB
[13] SPE
[12] EPE
[11] PBE
Rev. 1.10
30 29 28
22 21 20
14 13 12
BCB SPE EPE
0 RW 0 RW
6 5 4
URTXEN
0 RW 0 RW
Descriptions
Request-To-Send Signal
0: Drive USART RTS pin to logic 1
1: Drive USART RTS pin to logic 0
Note that the RTS bit is used to control the USART RTS pin status when the HFCEN
bit is reset.
When the HFCEN bit is set, this RTS bit indicates the pin status that is controlled by
hardware flow control function.
Break Control Bit
When this bit is set 1, the serial data output on the USART TX pin will be forced to
the Spacing State (logic 0). This bit acts only on USART TX output pin and has no
effect on the transmitter logic.
Stick Parity Enable
0: Disable stick parity
1: Stick Parity bit is transmitted
This bit is only available when the PBE bit is set to 1. If both the PBE and SPE bits
are set to 1 and the EPE bit is cleared to 0, the transmitted parity bit will be stuck to
1. However, when the PBE and SPE bits are set to 1 and also the EPE bit is set to 1,
the transmitted parity bit will be stuck to 0.
Even Parity Enable
0: Odd number of logic 1's are transmitted or checked in the data word and parity
bits.
1: Even number of logic 1's are transmitted or checked in the data word and
parity bits.
This bit is only available when PBE is set to 1.
Parity Bit Enable
0: Parity bit is not generated (transmitted data) or checked (receive data) during
transfer
1: Parity bit is generated or checked during transfer
Note: When the WLS field is set to "10" to select the 9-bit data format, writing to the
PBE bit has no effect.
443 of 590
27 26
Reserved
19 18
Reserved
11 10
PBE NSB
0 RW 0 RW 0 RW
3 2
HFCEN TRSM
0 RW 0 RW 0 RW
25 24
17 16
9 8
WLS
0 RW 0
1 0
MODE
0 RW 0
November 28, 2018