Adc Regular Conversion Mode Register - Adcconv - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
ADC Regular Conversion Mode Register – ADCCONV
This register specifies the mode setting, queue length, and subgroup length of ADC regular conversion mode.
Note that once the content of ADCCONV is changed, the regular conversion in progress will be aborted and ADC
will be reset. Firmware has to wait for at least one ADCLK before issuing the next command.
Offset: 0x008
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
ADCEN
Type/Reset RW 0
Bits Field
[18:16] ADSUBL
[10:8] ADSEQL
[7] ADCEN
[1:0] ADMODE
Rev. 1.10
30 29 28
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
ADC Regular Conversion Subgroup Length
ADSUBL specifies the conversion channel length of each subgroup for regular
discontinuous mode. Length of each subgroup = ADSUBL [2:0] + 1. If (ADSEQL [2:0]
+ 1) is not a multiple of (ADSUBL [2:0] + 1), the last subgroup will be shorter than
others.
ADC Regular Conversion Length
0x00: Implement a conversion on the specified channel only (specified by
ADSEQ0 in ADCLST0 register)
Others: Length of list queue = ADSEQL [2:0] + 1
ADC Enable
0: ADC disable
1: ADC enable
ADC Regular Conversion Mode
ADMODE [1:0] Mode
00 One shot mode
01 Reserved
Continuous
10
mode
Discontinuous
11
mode
194 of 590
27 26
Reserved
19 18
ADSUBL
RW 0 RW
11 10
ADSEQL
RW 0 RW
3 2
RW
Descriptions
After a start trigger, the conversion will be
executed on the specific channels for the whole
conversion sequence once.
—
After a start trigger, the conversion will be
executed on the specific channels for the whole
sequence continuously until conversion mode
is changed.
After a start trigger, the conversion will be
executed on the current subgroup. When the
last subgroup is finished, the conversion will
restart from the first subgroup if another start
trigger occurs.
25 24
17 16
0 RW 0
9 8
0 RW 0
1 0
ADMODE
0 RW 0
November 28, 2018