Holtek HT32F12345 User Manual page 23

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Figure 81. Update Event 1 Dependent Repetition Mechanism Example .............................................. 295
Figure 82. MCTM Clock Selection Source ............................................................................................ 296
Figure 83. Trigger Control Block ........................................................................................................... 297
Figure 84. Slave Controller Diagram .................................................................................................... 298
Figure 85. MCTM in Restart Mode ....................................................................................................... 298
Figure 86. MCTM in Pause Mode ......................................................................................................... 299
Figure 87. MCTM in Trigger Mode ........................................................................................................ 299
Figure 88. Master MCTMn and Slave GPTMm/MCTMm Connection .................................................. 300
Figure 89. MTO Selection ..................................................................................................................... 300
Figure 90. Capture / Compare Block Diagram ...................................................................................... 301
Figure 91. Input Capture Mode ............................................................................................................. 301
Figure 92. PWM Pulse Width Measurement Example .......................................................................... 302
Figure 93. Channel 0 and Channel 1 Input Stages ............................................................................... 303
Figure 94. Channel 2 and Channel 3 Input Stages ............................................................................... 303
Figure 95. Output Stage Block Diagram ............................................................................................... 304
Figure 96. Toggle Mode Channel Output Reference Signal - CHxPRE = 0 ......................................... 305
Figure 97. Toggle Mode Channel Output Reference Signal - CHxPRE = 1 ......................................... 306
Figure 98. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 306
Figure 99. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 307
Figure 100. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting
Mode ...................................................................................................................................................... 307
Figure 101. Dead-time Insertion Performed for Complementary Outputs ............................................ 308
Figure 102. MCTM Break Signal Bolck Diagram ................................................................................. 309
Figure 103. MTn_BRK Pin Digital Filter Diagram with N = 2 ................................................................ 309
Figure 104. Channel 3 Output with a Break Event Occurrence ............................................................ 310
Figure 105. Channel 0 ~ 2 Complementary Outputs with a Break Event Occurrence...........................311
Figure 106. Channel 0 ~ 2 Only One Output Enabled when Break Event Occurs ................................311
Figure 107. Hardware Protection When Both CHxO and CHxNO Are in Active Condition ................... 312
Figure 108. Update Event 1 Setup Diagram ......................................................................................... 314
Figure 109. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 314
Figure 110. Update Event 2 Setup Diagram ......................................................................................... 315
Figure 111. Input Stage and Quadature Decoder Block Diagram ......................................................... 315
Figure 112. Both TI0 and TI1 Quadrature Decoder Counting ............................................................... 316
Figure 113. MTn_ETI Pin Digital Filter Diagram with N = 2 .................................................................. 317
Figure 114. Clearing CHxOREF by ETIF .............................................................................................. 317
Figure 115. Single Pulse Mode ............................................................................................................. 318
Figure 116. Immediate Active Mode Minimum Delay ............................................................................ 319
Figure 117. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 320
Figure 118. Pausing GPTM0 Using the MCTM0 CH0OREF Signal ..................................................... 321
Figure 119. Triggering GPTM0 with MCTM0 Update Event 1............................................................... 321
Figure 120. Trigger MCTM0 and GPTM0 with the MCTM0 CH0 Input ................................................. 322
Rev. 1.10 23 of 590 November 28, 2018