Holtek HT32F12345 User Manual page 16

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Register Map ..................................................................................................................... 549
Register Descriptions ......................................................................................................... 550
I 2 S Control Register - I2SCR ........................................................................................................ 550
I 2 S Interrupt Enable Register - I2SIER ......................................................................................... 552
I 2 S Clock Divider Register - I2SCDR ........................................................................................... 553
I 2 S TX Data Register - I2STXDR ................................................................................................. 554
I S RX Data Register - I2SRXDR ................................................................................................. 554
2
I 2 S FIFO Control Register - I2SFCR ............................................................................................ 555
I 2 S Status Register - I2SSR ......................................................................................................... 556
I 2 S Rate Counter Value Register - I2SRCNTR ............................................................................ 558
27 Cyclic Redundancy Check (CRC) .................................................................... 559
Introduction ....................................................................................................................... 559
Features ............................................................................................................................. 559
Functional Descriptions ..................................................................................................... 560
CRC Computation ......................................................................................................................... 560
Byte and Bit Reversal for CRC Computation ................................................................................ 560
CRC with PDMA ........................................................................................................................... 561
Register Map ..................................................................................................................... 561
Register Descriptions ......................................................................................................... 562
CRC Control Register - CRCCR .................................................................................................. 562
CRC Seed Register - CRCSDR ................................................................................................... 563
CRC Checksum Register - CRCCSR .......................................................................................... 563
CRC Data Register - CRCDR ...................................................................................................... 564
28 SDIO Host Controller (SDIO) ............................................................................ 565
Introduction ........................................................................................................................ 565
Features ............................................................................................................................. 565
Functional Description ....................................................................................................... 565
SD Clock ....................................................................................................................................... 566
SD Protocol ................................................................................................................................... 567
Command ..................................................................................................................................... 568
Response ...................................................................................................................................... 568
Data .............................................................................................................................................. 569
Buffer Status ................................................................................................................................. 571
Interrupt ........................................................................................................................................ 571
DMA Request ................................................................................................................................ 571
Register Map ..................................................................................................................... 572
Register Description .......................................................................................................... 573
Block Size Register - BLSIZE ...................................................................................................... 573
Block Count Register - BLCNT .................................................................................................... 574
Argument Register - ARG ............................................................................................................ 574
Transfer Mode Register - TMR .................................................................................................... 575
Command Register - CMD ........................................................................................................... 576
Rev. 1.10 16 of 590 November 28, 2018