Pdma Interrupt Enable Register 1 - Pdmaier1 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[ 2 6 ] , [ 2 1 ] , BEIEn
[16], [11], [6],
[1]
[ 2 5 ] , [ 2 0 ] , GEIEn
[ 1 5 ] , [ 1 0 ] ,
[5], [0]
PDMA Interrupt Enable Register 1 – PDMAIER1
This register is used to enable or disable the related interrupts of the PDMA channel 6 ~ 11.
Offset: 0x134
Reset value: 0x0000_0000
31
Reserved
Type/Reset
23
TCIE10
Type/Reset RW 0 RW
15
GEIE9
Type/Reset RW 0 RW
7
HTIE7
Type/Reset RW 0 RW
Bits Field
[ 2 9 ] , [ 2 4 ] , TEIEn
[ 1 9 ] , [ 1 4 ] ,
[9], [4]
[ 2 8 ] , [ 2 3 ] , TCIEn
[ 1 8 ] , [ 1 3 ] ,
[8], [3]
[ 2 7 ] , [ 2 2 ] , HTIEn
[ 1 7 ] , [ 1 2 ] ,
[7], [2]
[ 2 6 ] , [ 2 1 ] , BEIEn
[16], [11], [6],
[1]
[ 2 5 ] , [ 2 0 ] , GEIEn
[ 1 5 ] , [ 1 0 ] ,
[5], [0]
Rev. 1.10
Descriptions
Channel n Block Transaction End Interrupt Enable control (n = 0 ~ 5)
0: Block Transaction End interrupt is disabled
1: Block Transaction End interrupt is enabled
This bit is set and cleared by software.
Channel n Global Transfer Event Interrupt Enable control (n = 0 ~ 5)
0: Global Transfer Event interrupt is disabled
1: Global Transfer Event interrupt is enabled
This bit is set and cleared by software.
30 29 28
TEIE11 TCIE11
RW 0 RW
22 21 20
HTIE10 BEIE10 GEIE10
0 RW 0 RW
14 13 12
TEIE8 TCIE8 HTIE8
0 RW 0 RW
6 5
BEIE7 GEIE7 TEIE6
0 RW 0 RW
Descriptions
Channel n Transfer Error Interrupt Enable control (n = 6 ~ 11)
0: Transfer Error interrupt is disabled
1: Transfer Error interrupt is enabled
This bit is set and cleared by software.
Channel n Transfer Complete Interrupt Enable control (n = 6 ~ 11)
0: Transfer Completion interrupt is disabled
1: Transfer Completion interrupt is enabled
This bit is set and cleared by software.
Channel n Half Transfer Interrupt Enable control (n = 6 ~ 11)
0: Half Transfer interrupt is disabled
1: Half Transfer interrupt is enabled
This bit is set and cleared by software.
Channel n Block Transaction End Interrupt Enable control (n = 6 ~ 11)
0: Block Transaction End interrupt is disabled
1: Block Transaction End interrupt is enabled
This bit is set and cleared by software.
Channel n Global Transfer Event Interrupt Enable control (n = 6 ~ 11)
0: Global Transfer Event interrupt is disabled
1: Global Transfer Event interrupt is enabled
This bit is set and cleared by software.
513 of 590
27 26
HTIE11 BEIE11
0 RW 0 RW
19 18
TEIE9 TCIE9
0 RW 0 RW
11 10
BEIE8 GEIE8
0 RW 0 RW
4 3 2
TCIE6 HTIE6
0 RW 0 RW
25 24
GEIE11 TEIE10
0 RW 0 RW 0
17 16
HTIE9 BEIE9
0 RW 0 RW 0
9 8
TEIE7 TCIE7
0 RW 0 RW 0
1 0
BEIE6 GEIE6
0 RW 0 RW 0
November 28, 2018