Register Descriptions; Global Reset Status Register - Grsr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Register Descriptions

Global Reset Status Register
This register specifies a variety of reset status conditions.
Offset: 0x100
Reset value: 0x0000_0008
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[3] PORSTF
[2] WDTRSTF
[1] EXTRSTF
[0] SYSRSTF
Rev. 1.10
– GRSR
30 29 28
22 21 20
14 13 12
6 5 4
Reserved
Descriptions
Core Power On Reset Flag
0: No POR occurred
1: POR occurred
This bit is set by hardware when a power on reset occurs and reset by writing 1
into it.
Watchdog Timer Reset Flag
0: No Watchdog Timer reset occurred
1: Watchdog Timer occurred
This bit is set by hardware when a watchdog timer reset occurs and reset by
writing 1 into it or by hardware when a power on reset occurs.
External Pin Reset Flag
0: No pin reset occurred
1: Pin reset occurred
This bit is set by hardware when an external pin reset occurs and reset by writing
1 into it or by hardware when a power on reset occurs.
System Reset Flag
0: No NVIC asserting system reset occurred
1: NVIC asserting system reset occurred
This bit is set by hardware when a system reset occurs and reset by writing 1 into
it or by hardware when a power on reset occurs.
119 of 590
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
PORSTF WDTRSTF EXTRSTF SYSRSTF
WC 1 WC 0 WC
25 24
17 16
9 8
1 0
0 WC 0
November 28, 2018