Pdma Interrupt Status Clear Register 1 - Pdmaiscr1 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[ 2 7 ] , [ 2 2 ] , HTRICLRn
[ 1 7 ] , [ 1 2 ] ,
[7], [2]
[ 2 6 ] , [ 2 1 ] , BEICLRn
[16], [11], [6],
[1]
[ 2 5 ] , [ 2 0 ] , GEICLRn
[ 1 5 ] , [ 1 0 ] ,
[5], [0]
PDMA Interrupt Status Clear Register 1 – PDMAISCR1
This register is used to clear the corresponding interrupt status bits in the PDMAISR1 Register.
Offset: 0x12C
Reset value: 0x0000_0000
31
Reserved
Type/Reset
23
TCICLR10 HTICLR10 BEICLR10 GEICLR10 TEICLR9
Type/Reset WC 0 WC
15
GEICLR9 TEICLR8
Type/Reset WC 0 WC
7
HTICLR7 BEICLR7
Type/Reset WC 0 WC
Bits Field
[ 2 9 ] , [ 2 4 ] , TEICLRn
[ 1 9 ] , [ 1 4 ] ,
[9], [4]
[ 2 8 ] , [ 2 3 ] , TCICLRn
[ 1 8 ] , [ 1 3 ] ,
[8], [3]
Rev. 1.10
Descriptions
Channel n Half Transfer Interrupt Status Clear (n = 0 ~ 5)
0: No Operation
1: Clear the corresponding HTISTAn bit in the PDMAISR0 register
Writing a "1" into the HTRICLRn bit will clear the HTISTAn status bit in the
PDMAISR0 register. This bit will be automatically cleared to 0 after a "1" is written.
Channel n Block Transaction End Interrupt Status Clear (n = 0 ~ 5)
0: No Operation
1: Clear the corresponding BEISTAn bit in the PDMAISR0 register
Writing a "1" into the BEICLRn bit will clear the BEISTAn status bit in the PDMAISR0
register. This bit will be automatically cleared to 0 after a data "1" is written.
Channel n Global Transfer Event Interrupt Status Clear (n = 0 ~ 5)
0: No Operation
1: Clear the corresponding TEISTAn, TCISTAn, HTISTAn, BEISTAn, and
GEISTAn bits in the PDMAISR0 register
Writing a "1" into the GEICLRn bit will clear the GEISTAn status bit together with the
TEISTAn, TCISTAn, HTISTAn, BEISTAn bits in the PDMAISR0 register. This bit will
be automatically cleared to 0 after a "1" is written.
30 29 28
TEICLR11 TCICLR11 HTICLR11 BEICLR11 GEICLR11 TEICLR10
WC 0 WC
22 21 20
0 WC 0 WC
14 13 12
TCICLR8 HTICLR8
0 WC 0 WC
6 5
GEICLR7 TEICLR6
0 WC 0 WC
Descriptions
Channel n Transfer Error Interrupt Status Clear (n = 6 ~ 11)
0: No Operation
1: Clear the corresponding TEISTAn bit in the PDMAISR1 register
Writing a "1" into the TEICLRn bit will clear the TEISTAn status bit in the PDMAISR1
register. This bit will be automatically cleared to 0 after a "1" is written.
Channel n Transfer Complete Interrupt Status Clear (n = 6 ~ 11)
0: No Operation
1: Clear the corresponding TCISTAn bit in the PDMAISR1 register
Writing a "1" into the TCICLRn bit will clear the TCISTAn status bit in the PDMAISR1
register. This bit will be automatically cleared to 0 after a "1" is written.
511 of 590
27 26
0 WC 0 WC
19 18
TCICLR9
0 WC 0 WC
11 10
BEICLR8 GEICLR8
0 WC 0 WC
4 3 2
TCICLR6 HTICLR6
0 WC 0 WC
25 24
0 WC 0 WC 0
17 16
HTICLR9 BEICLR9
0 WC 0 WC 0
9 8
TEICLR7 TCICLR7
0 WC 0 WC 0
1 0
BEICLR6 GEICLR6
0 WC 0 WC 0
November 28, 2018