32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
General Call Address
The general call addressing function can be used to address all the devices connected to the I
bus. The master device can activate the general call function by writing a value "00" into the TAR
and setting the RWD bit to 0 in the I2CTAR register on the addressing frame.
The device can support the general call addressing function by setting the corresponding enable
control bit GCEN to 1. If the GCEN bit is set to 1 to support the general call addressing, the AA bit
in the I2CCR register should also be set to 1 to send an acknowledge signal back when the device
receives an address frame with a value of 00H. When this condition occurs, the general call flag,
GCS, will be set to 1, but the ADRS flag will not be set.
Bus Error
If an unpredictable START or STOP condition occurs when the data is being transferred on the I
bus, it will be considered as a bus error and the transferring data will be aborted. When a bus error
event occurs, the relevant bus error flag BUSERR in the I2CSR register will set to 1 and both the
SDA and SCL lines are released. The BUSERR flag should be cleared by writing a 1 to it to initiate
the I
2
C module to an idle state.
Address Mask Enable
The I
C module provides address mask function for user to decide which address bit can be ignored
2
during the comparison with the address frame sent from the master. The ADRS flag will be
asserted when the unmasked address bits and the address frame sent from the master are matched.
Note that this function is only available in the slave mode.
For instance, the user sets a data transfer with 7-bit addressing mode together with the I2CADDMR
register value as 0x05h and the I2CADDR register value as 0x55h, this means if an address which
is sent by an I
2
C master on the bus is equal to 0x50h, 0x51h, 0x54h or 0x55h, the I
will all be considered to be matched and the ADRS flag in the I2CSR register will be asserted after
the address frame.
Address Snoop
The Address Snoop register, I2CADDSR, is used to monitor the calling address on the I
during the whole data transfer operation no matter if the I
device. Note that the I2CADDSR register is a read only register and each calling address on the I
bus will be stored in the I2CADDSR register automatically even if the I
Operation Mode
The I
C module can operate in one of the following modes:
2
▄
Master Transmitter
▄
Master Receiver
▄
Slave Transmitter
▄
Slave Receiver
The I
C module operates in the slave mode by default. The interface will switch to the master mode
2
automatically after generating a START signal.
Rev. 1.10
2
C module operates as a master or a slave
390 of 590
2
C
2
C
2
C slave address
2
C bus
C
2
2
C device is not addressed.
November 28, 2018
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