Adc High Priority Conversion Mode Register - Adchconv - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
ADC High Priority Conversion Mode Register – ADCHCONV
This register specifies the mode setting, queue length, and subgroup length of ADC high priority conversion
mode. Note that once the content of ADCHCONV is changed, the high priority conversion in progress will be
aborted and ADC will be reset. Firmware has to wait for at least one ADCLK before issuing the next command.
Offset: 0x00C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field Descriptions
[17:16] ADHSUBL ADC High Priority Conversion Subgroup Length
ADHSUBL specifies the conversion channel length of each subgroup for high priority
discontinuous mode. Length of each subgroup = ADHSUBL [1:0] + 1. If (ADHSEQL
[1:0] + 1) is not a multiple of (ADHSUBL [1:0] + 1), the last subgroup will be shorter
than others.
[9:8] ADHSEQL ADC High Priority Conversion Length
[1:0] ADHMODE ADC High Priority Conversion Mode
Rev. 1.10
30 29 28
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
0x00: Implement a conversion on the specified channel only (specified by
ADHSEQ0 in ADCHLST)
Others: Length of list queue = ADHSEQL [1:0] + 1
ADHMODE [1:0] Mode
00 One shot mode
01 Reserved
Continuous
10
mode
Discontinuous
11
mode
195 of 590
27 26 25
Reserved
19 18 17
RW
11 10 9
RW
3 2 1
RW
Descriptions
After a start trigger, the conversion will be
executed on the specific channels for the whole
conversion sequence once.
—
After a start trigger, the conversion will be
executed on the specific channels for the whole
sequence continuously until conversion mode
is changed.
After a start trigger, the conversion will be
executed on the current subgroup. When the
last subgroup is finished, the conversion will
restart from the first subgroup if another start
trigger occurs.
24
16
ADHSUBL
0 RW 0
8
ADHSEQL
0 RW 0
0
ADHMODE
0 RW 0
November 28, 2018