32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
23
USB Device Controller (USB)
Introduction
The USB device controller is compliant with the USB 2.0 full-speed specification. There is one
control endpoint know as Endpoint 0 and seven configurable endpoints (EP1 ~ EP7). A 1024-
byte EP_SRAM is used for the endpoint buffers. Each endpoint buffer size is programmable
by corresponding registers, which provides maximum flexibility for various applications. The
integrated USB full-speed transceiver helps to minimize overall system complexity and cost. The
USB also contains suspend and resume features to meet low-power consumption requirement. The
accompanying figure shows the USB block diagram.
Registers
256
EP_SRAM
HCLK
48 MHz_CLK
Interrupt
Figure 164. USB Block Diagram
Features
▄
Complies with USB 2.0 full-speed (12 Mbps) specification
▄
Fully integrated USB full-speed transceiver
▄
1 control endpoint (EP0) for control transfer
▄
3 single-buffered endpoint (EP1 ~ EP3) for bulk and interrupt transfer
▄
4 double-buffered endpoint (EP4 ~ EP7) for bulk, interrupt and isochronous transfer
▄
1,024 bytes EP_SRAM used as endpoint data buffers
Rev. 1.10
Control Logic
Endpoint 0
Ctrl
IN and OUT
Endpoint type A
32-bit
Int/Bulk
IN or OUT
Endpoint type B
Int/Bulk/Iso
IN or OUT
USB Device Controller (USB)
467 of 590
Serial
On-chip
Interface
USB Full-Speed
Engine
Transceiver
(SIE)
November 28, 2018
DP
DM
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