Apb Clock Control Register 1 - Apbccr1 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[5] SPI1EN
[4] SPI0EN
[1] I2C1EN
[0] I2C0EN
APB Clock Control Register 1 – APBCCR1
This register specifies the APB peripherals clock enable bits.
Offset: 0x030
Reset value: 0x0000_0000
31
Type/Reset
23
Reserved
Type/Reset RW
15
Type/Reset
7
Reserved BKPREN
Type/Reset RW
Bits Field
[24] ADCCEN
[22] CMPEN
[17] BFTM1EN
Rev. 1.10
Descriptions
SPI1 Clock Enable
0: SPI1 clock is disabled
1: SPI1 clock is enabled
Set and reset by software.
SPI0 Clock Enable
0: SPI0 clock is disabled
1: SPI0 clock is enabled
Set and reset by software.
I 2 C1 Clock Enable
0: I 2 C1 clock is disabled
1: I 2 C1 clock is enabled
Set and reset by software.
I 2 C0 Clock Enable
0: I 2 C0 clock is disabled
1: I 2 C0 clock is enabled
Set and reset by software.
30 29 28
Reserved
22 21 20
CMPEN
0
14 13 12
Reserved
6 5
Reserved WDTREN
0 RW
Descriptions
ADC Controller Clock Enable
0: ADC clock is disabled
1: ADC clock is enabled
Set and reset by software.
CMP Clock Enable
0: CMP clock is disabled
1: CMP clock is enabled
Set and reset by software.
BFTM1 Clock Enable
0: BFTM1 clock is disabled
1: BFTM1 clock is enabled
Set and reset by software.
106 of 590
27 26
19 18
Reserved
11 10
4 3 2
Reserved MCTM1EN MCTM0EN
0
25 24
ADCCEN
RW 0
17 16
BFTM1EN BFTM0EN
RW 0 RW 0
9 8
GPTM1EN GPTM0EN
RW 0 RW 0
1 0
RW 0 RW 0
November 28, 2018