Status Register - Sr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Status Register – SR
This register contains the host controller status bits.
Offset: 0x044
Reset value: 0x0000_0000
31
Type/Reset
23
Reserved
Type/Reset
15
ERRSTA
Type/Reset RO 0
7
BESTA
Type/Reset WC 0 WC
Bits Field
[26] CICESTA
[25] CIDESTA
[24] CISTA
[22] DEESTA
[21] DCESTA
Rev. 1.10
30 29
Reserved
22 21
DEESTA DCESTA DTESTA
WC 0 WC 0 WC
14 13
6 5
BFSTA BHSTA BUSTA
0 WC 0 WC
Descriptions
Command Inhibit (CMD) Error Status
0: No Error
1: Error
This bit will be set to 1 when writing to the Command Register or Argument
Register when Command Inhibit (CMD) is high.
Command Inhibit (DAT) Error Status
0: No Error
1: Error
This bit will be set to 1 when writing to the Command Register (which uses the
DAT line), Block Size Register and Transfer Mode Register when Command
Inhibit (DAT) is high.
Card Interrupt Status
0: No Card Interrupt
1: Generate Card Interrupt
When the host controller is sampling, a card interrupt from the SD device will
set this bit to 1.
Data End Bit Error Status
0: No Error
1: Error
Occurs either when detecting 0 at the end bit position of the read data which
uses the DAT line or at the end bit position of the CRC Status.
Data CRC Error Status
0: No Error
1: Error
Occurs when detecting a CRC error during the transfer of read data which
uses the DAT lines or when detecting the Write CRC status having a value
other than "010".
584 of 590
28 27 26
CICESTA
WC
20 19 18
CIESTA CEESTA
0 WC 0 WC
12 11 10
Reserved
4 3 2
BOSTA Reserved
0 WC 0
25 24
CIDESTA CISTA
0 WC 0 RO 0
17 16
CCESTA CTESTA
0 WC 0 WC 0
9 8
1 0
TCSTA CCSTA
WC 0 WC 0
November 28, 2018