32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Block Count Register – BLCNT
This register is used to configure the number of data blocks.
Offset:
0x004
Reset value:
0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Bits
Field
[15:0]
BLCNT
Argument Register – ARG
This register contains the SD command argument.
Offset:
0x008
Reset value:
0x0000_0000
31
Type/Reset
RW
0 RW
23
Type/Reset
RW
0 RW
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Rev. 1.10
30
29
28
22
21
20
14
13
12
0 RW
0 RW
6
5
4
0 RW
0 RW
Descriptions
Blocks Count for Current transfer
0000h: Stop Count
0001h: 1 block
0002h: 2 blocks
...
FFFFh: 65535 blocks
This register is enabled when Block Count Enable in the Transfer Mode register is
set to 1 and is valid only for multiple block transfers.
30
29
28
0 RW
0 RW
22
21
20
0 RW
0 RW
14
13
12
0 RW
0 RW
6
5
4
0 RW
0 RW
574 of 590
27
26
Reserved
19
18
Reserved
11
10
BLCNT
0 RW
0 RW
0 RW
3
2
BLCNT
0 RW
0 RW
0 RW
27
26
ARG
0 RW
0 RW
0 RW
19
18
ARG
0 RW
0 RW
0 RW
11
10
ARG
0 RW
0 RW
0 RW
3
2
ARG
0 RW
0 RW
0 RW
25
24
17
16
9
8
0 RW
0
1
0
0 RW
0
25
24
0 RW
0
17
16
0 RW
0
9
8
0 RW
0
1
0
0 RW
0
November 28, 2018
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